From 681ef51d731617a0a4d5b604d561acdecb9c9cfa Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 11 Feb 2018 01:17:01 -0600 Subject: drivers/intel/gma: fix opregion SCI register for Atom platforms Most Intel platforms use separate registers for software-based SMI (0xe0) and SCI (0xe8), but Atom-based platforms use a single combined register (0xe0) for both. Adjust opregion implementation to use the correct register for Atom-based platforms. Test: Boot Windows on Atom-based ChromeOS device with Tianocore payload and non-VBIOS graphics init; observe Intel display driver loaded correctly and internal display not blank. (requires additional change for Atom platforms to select CONFIG_INTEL_GMA_SWSMISCI) Change-Id: I636986226ff951dae637dca5bc3ad0e023d94243 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/23696 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/drivers/intel/gma/opregion.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'src/drivers/intel/gma/opregion.c') diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 74c629c9c2..b939b88324 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -32,6 +32,7 @@ void intel_gma_opregion_register(uintptr_t opregion) { device_t igd; u16 reg16; + u16 sci_reg; igd = dev_find_slot(0, PCI_DEVFN(0x2, 0)); if (!igd || !igd->enabled) @@ -43,15 +44,24 @@ void intel_gma_opregion_register(uintptr_t opregion) */ pci_write_config32(igd, ASLS, opregion); + /* + * Atom-based platforms use a combined SMI/SCI register, + * whereas non-Atom platforms use a separate SCI register. + */ + if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI)) + sci_reg = SWSMISCI; + else + sci_reg = SWSCI; + /* * Intel's Windows driver relies on this: * Intel BIOS Specification * Chapter 5.4 "ASL Software SCI Handler" */ - reg16 = pci_read_config16(igd, SWSCI); + reg16 = pci_read_config16(igd, sci_reg); reg16 &= ~GSSCIE; reg16 |= SMISCISEL; - pci_write_config16(igd, SWSCI, reg16); + pci_write_config16(igd, sci_reg, reg16); } /* Restore ASLS register on S3 resume and prepare SWSCI. */ -- cgit v1.2.3