From 746aa054e2633e3c328631ea0d50bec31460f9e7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 20 May 2017 02:47:37 +0200 Subject: drivers/intel/gma: Drop unused INTEL_DP Change-Id: I786848cd48c6fcfecf9b72c60623cadcfcbb7db7 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/19803 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/drivers/intel/gma/intel_ddi.c | 156 -------------------------------------- 1 file changed, 156 deletions(-) (limited to 'src/drivers/intel/gma/intel_ddi.c') diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 9127060ece..c01aef45c9 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -114,159 +114,3 @@ void intel_prepare_ddi(void) intel_prepare_ddi_buffers(PORT_E, use_fdi); } - -static void intel_wait_ddi_buf_idle(int port) -{ - uint32_t reg = DDI_BUF_CTL(port); - int i; - - for (i = 0; i < 8; i++) { - udelay(1); - if (gtt_read(reg) & DDI_BUF_IS_IDLE){ - printk(BIOS_SPEW, "%s: buf is idle (success)\n", __func__); - return; - } - } - printk(BIOS_ERR, "Timeout waiting for DDI BUF %d idle bit\n", port); -} - - -void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port) -{ - int wait = 0; - uint32_t val; - - if (gtt_read(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { - val = gtt_read(DDI_BUF_CTL(port)); - if (val & DDI_BUF_CTL_ENABLE) { - val &= ~DDI_BUF_CTL_ENABLE; - gtt_write(val,DDI_BUF_CTL(port)); - wait = 1; - } - - val = gtt_read(DP_TP_CTL(port)); - val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); - val |= DP_TP_CTL_LINK_TRAIN_PAT1; - gtt_write(val,DP_TP_CTL(port)); - //POSTING_READ(DP_TP_CTL(port)); - - if (wait) - intel_wait_ddi_buf_idle(port); - } - - val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | - DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; - if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) - val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; - gtt_write(val,DP_TP_CTL(port)); - //POSTING_READ(DP_TP_CTL(port)); - - intel_dp->DP |= DDI_BUF_CTL_ENABLE; - gtt_write(intel_dp->DP,DDI_BUF_CTL(port)); - //POSTING_READ(DDI_BUF_CTL(port)); - - udelay(600); -} - -u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp, - enum port port, - enum pipe pipe, - int type, - int lane_count, - int pf_sz, - u8 phsync, - u8 pvsync) -{ - u32 temp; - - temp = TRANS_DDI_FUNC_ENABLE; - temp |= TRANS_DDI_SELECT_PORT(port); - - switch (pipe_bpp) { - case 18: - temp |= TRANS_DDI_BPC_6; - break; - case 24: - temp |= TRANS_DDI_BPC_8; - break; - case 30: - temp |= TRANS_DDI_BPC_10; - break; - case 36: - temp |= TRANS_DDI_BPC_12; - break; - default: - printk(BIOS_ERR, "Invalid pipe_bpp: %d, *** Initialization will not succeed ***\n", pipe_bpp); - } - - if (port == PORT_A) { - switch (pipe) { - case PIPE_A: - if (pf_sz) - temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; - else - temp |= TRANS_DDI_EDP_INPUT_A_ON; - break; - case PIPE_B: - temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; - break; - case PIPE_C: - temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; - break; - default: - printk(BIOS_ERR, "Invalid pipe %d\n", pipe); - } - } - - if (phsync) - temp |= TRANS_DDI_PHSYNC; - - if (pvsync) - temp |= TRANS_DDI_PVSYNC; - - if (type == INTEL_OUTPUT_HDMI) { - /* Need to understand when to set TRANS_DDI_MODE_SELECT_HDMI / TRANS_DDI_MODE_SELECT_DVI */ - } else if (type == INTEL_OUTPUT_ANALOG) { - /* Set TRANS_DDI_MODE_SELECT_FDI with lane_count */ - } else if (type == INTEL_OUTPUT_DISPLAYPORT || - type == INTEL_OUTPUT_EDP) { - temp |= TRANS_DDI_MODE_SELECT_DP_SST; - - temp |= DDI_PORT_WIDTH(lane_count); - } else { - printk(BIOS_ERR, "Invalid type %d for pipe\n", type); - } - - return temp; -} - -enum transcoder intel_ddi_get_transcoder(enum port port, - enum pipe pipe) -{ - if (port == PORT_A) - return TRANSCODER_EDP; - return (enum transcoder)pipe; -} - -void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp) -{ - u32 val = TRANS_MSA_SYNC_CLK; - - switch (intel_dp->pipe_bits_per_pixel) { - case 18: - val |= TRANS_MSA_6_BPC; - break; - case 24: - val |= TRANS_MSA_8_BPC; - break; - case 30: - val |= TRANS_MSA_10_BPC; - break; - case 36: - val |= TRANS_MSA_12_BPC; - break; - default: - printk(BIOS_ERR, "Invalid bpp settings %d\n", intel_dp->pipe_bits_per_pixel); - } - gtt_write(TRANS_MSA_MISC(intel_dp->transcoder),val); -} -- cgit v1.2.3