From 45df5962c7044713f4631f9483426d9241e36bde Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Mon, 8 Jul 2013 14:02:57 -0700 Subject: SLIPPY: final changes for FUI The intel_ddi.c change I thought should be in but I don't see it. It just adds two functions back that we need. There are two new files for slippy annotated with comments about how it needs to evolve. That said, this code has been tested on 3 different panels. Both dev and non-dev usages work. physbase initialization to static value removed. Moved spin calls to intel_dp_* Change-Id: I0480af45c21c7dedcaff7e8be729f0eb554ec78a Signed-off-by: Ronald G. Minnich Reviewed-on: https://gerrit.chromium.org/gerrit/61136 Commit-Queue: Ronald G. Minnich Reviewed-by: Ronald G. Minnich Tested-by: Ronald G. Minnich Reviewed-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/4370 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/drivers/intel/gma/intel_ddi.c | 52 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'src/drivers/intel/gma/intel_ddi.c') diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 659d73ca04..220bd47100 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -105,3 +105,55 @@ void intel_prepare_ddi_buffers(int port, int use_fdi_mode) } } +static void intel_wait_ddi_buf_idle(int port) +{ + uint32_t reg = DDI_BUF_CTL(port); + int i; + + for (i = 0; i < 8; i++) { + udelay(1); + if (io_i915_read32(reg) & DDI_BUF_IS_IDLE){ + printk(BIOS_SPEW, "%s: buf is idle (success)\n", __func__); + return; + } + } + printk(BIOS_ERR, "Timeout waiting for DDI BUF %d idle bit\n", port); +} + + +void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port) +{ + int wait; + uint32_t val; + + if (io_i915_read32(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { + val = io_i915_read32(DDI_BUF_CTL(port)); + if (val & DDI_BUF_CTL_ENABLE) { + val &= ~DDI_BUF_CTL_ENABLE; + io_i915_write32(DDI_BUF_CTL(port), val); + wait = 1; + } + + val = io_i915_read32(DP_TP_CTL(port)); + val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); + val |= DP_TP_CTL_LINK_TRAIN_PAT1; + io_i915_write32(DP_TP_CTL(port), val); + //POSTING_READ(DP_TP_CTL(port)); + + if (wait) + intel_wait_ddi_buf_idle(port); + } + + val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | + DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; + if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) + val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; + io_i915_write32(DP_TP_CTL(port), val); + //POSTING_READ(DP_TP_CTL(port)); + + intel_dp->DP |= DDI_BUF_CTL_ENABLE; + io_i915_write32(DDI_BUF_CTL(port), intel_dp->DP); + //POSTING_READ(DDI_BUF_CTL(port)); + + udelay(600); +} -- cgit v1.2.3