From fa0725dead0fdc7e9330e77c42ff4ed4b36a89c4 Mon Sep 17 00:00:00 2001 From: Ryan Salsamendi Date: Fri, 30 Jun 2017 17:29:37 -0700 Subject: northbridge/intel/haswell: Fix undefined behavior Fix reports found by undefined behavior sanitizer. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56 Signed-off-by: Ryan Salsamendi Reviewed-on: https://review.coreboot.org/20447 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel --- src/drivers/intel/gma/i915_reg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/drivers/intel/gma/i915_reg.h') diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index dee6865224..e88ecfb87e 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -2979,7 +2979,7 @@ /* Ironlake */ #define CPU_VGACNTRL 0x41000 -#define CPU_VGA_DISABLE (1<<31) +#define CPU_VGA_DISABLE (1UL<<31) #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) @@ -4177,7 +4177,7 @@ #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ -#define HSW_PWR_WELL_ENABLE (1<<31) +#define HSW_PWR_WELL_ENABLE (1UL<<31) #define HSW_PWR_WELL_STATE (1<<30) #define HSW_PWR_WELL_CTL5 0x45410 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) -- cgit v1.2.3