From 1895838e7a3807a6fce324f0dfed193a3821f6df Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 7 Aug 2018 12:23:16 +0200 Subject: src/drivers: Fix typo Change-Id: I9144937b72a98517cbd41c093cff7bad543b4140 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27916 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/drivers/intel/gma/i915_reg.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/drivers/intel/gma/i915_reg.h') diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index ae774a549e..e0bf1427c5 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -609,7 +609,7 @@ #define LM_FIFO_WATERMARK 0x0000001F #define MI_ARB_STATE 0x020e4 /* 915+ only */ -/* Make render/texture TLB fetches lower priorty than associated data +/* Make render/texture TLB fetches lower priority than associated data * fetches. This is not turned on by default */ #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) @@ -1636,9 +1636,9 @@ #define BLM_PIPE_C (2 << 29) /* ivb + */ #define BLM_PIPE(pipe) ((pipe) << 29) #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ -#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) +#define BLM_PHASE_IN_INTERRUPT_STATUS (1 << 26) #define BLM_PHASE_IN_ENABLE (1 << 25) -#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) +#define BLM_PHASE_IN_INTERRUPT_ENABL (1 << 24) #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) #define BLM_PHASE_IN_COUNT_SHIFT (8) -- cgit v1.2.3