From 6b19071ffb89dbb68196b7f3b088d87d4fad9e80 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 22 Jul 2013 16:18:31 -0700 Subject: FUI: Fill in link_m and link_n values ... based on the EDID detailed timing values for pixel_clock and link_clock. Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n respectively. Other two undocumented registers 0x6f030 and 0x6f034 correspond to data_m and data_n respectively. Calculations are based on the intel_link_compute_m_n from linux kernel. Currently, the value for 0x6f030 does not come up right with our calculations. Hence, set to hard-coded value. Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e Reviewed-on: https://gerrit.chromium.org/gerrit/62915 Reviewed-by: Ronald G. Minnich Tested-by: Furquan Shaikh Commit-Queue: Furquan Shaikh Reviewed-on: http://review.coreboot.org/4381 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/drivers/intel/gma/i915.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/drivers/intel/gma/i915.h') diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index e976f912cc..62fe0230e6 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -65,6 +65,14 @@ void io_i915_write32(unsigned long val, unsigned long addr); #define DP_LINK_CONFIGURATION_SIZE 9 +struct intel_dp_m_n { + uint32_t tu; + uint32_t gmch_m; + uint32_t gmch_n; + uint32_t link_m; + uint32_t link_n; +}; + struct intel_dp { int gen; // 6 for link, 7 for wtm2 int has_pch_split; // 1 for link and wtm2 @@ -134,6 +142,7 @@ struct intel_dp { u32 pfa_ctl; u32 pipesrc; u32 stride; + struct intel_dp_m_n m_n; }; /* we may yet need these. */ @@ -183,3 +192,8 @@ void intel_dp_wait_reg(unsigned long addr, void intel_dp_wait_panel_power_control(unsigned long val); +void intel_dp_compute_m_n(unsigned int bits_per_pixel, + unsigned int nlanes, + unsigned int pixel_clock, + unsigned int link_clock, + struct intel_dp_m_n *m_n); -- cgit v1.2.3