From c58e3bd90a96bf01859d1c0af83926b1e17edff5 Mon Sep 17 00:00:00 2001 From: Keith Short Date: Fri, 10 May 2019 11:14:31 -0600 Subject: post_code: add post code for video initialization failure Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon initialization returns an error when graphics was also initialized. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/drivers/intel/fsp2_0/silicon_init.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'src/drivers/intel/fsp2_0') diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index b0a697d8cb..e9c29db40e 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -29,6 +30,7 @@ static void do_silicon_init(struct fsp_header *hdr) FSPS_UPD *upd, *supd; fsp_silicon_init_fn silicon_init; uint32_t status; + uint8_t postcode; supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); @@ -59,8 +61,18 @@ static void do_silicon_init(struct fsp_header *hdr) /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { + if (vbt_get()) { + /* Attempted to initialize graphics. Assume failure + * is related to a video failure. + */ + postcode = POST_VIDEO_FAILURE; + } else { + /* Other silicon initialization failed */ + postcode = POST_HW_INIT_FAILURE; + } printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); - die("FspSiliconINit returned an error!\n"); + die_with_post_code(postcode, + "FspSiliconINit returned an error!\n"); } } -- cgit v1.2.3