From 30a011417fb227d8e1e78a6a47abd9ea332c00c7 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 22 Mar 2023 00:35:42 +0530 Subject: soc/intel: Rename IA common code module from `TOM` to `RAMTOP` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch renames all references of `top_of_ram` (TOM) in IA common `basecode` module (for example: functions, variables, Kconfig, Makefile and comments) with `ramtop` aka top_of_ram to make it more meaningful and to avoid conflicts with Intel SA chipset TOM registers. BUG=Able to build and boot google/rex with the same ~49ms savings in place. Change-Id: Icfe6300a8e4c5761064537fb256cfecbe2afb2d8 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/73881 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/memory_init.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/drivers/intel/fsp2_0') diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 4f0dbf6148..6d25844b50 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -24,8 +24,8 @@ #include #include -#if CONFIG(SOC_INTEL_COMMON_BASECODE_TOM) -#include +#if CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP) +#include #endif static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); @@ -259,10 +259,10 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) die_with_post_code(POST_INVALID_VENDOR_BINARY, "FSPM_ARCH_UPD not found!\n"); - /* Early caching of TOM region if valid mrc cache data is found */ -#if (CONFIG(SOC_INTEL_COMMON_BASECODE_TOM)) + /* Early caching of RAMTOP region if valid mrc cache data is found */ +#if (CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP)) if (arch_upd->NvsBufferPtr) - early_tom_enable_cache_range(); + early_ramtop_enable_cache_range(); #endif /* Give SoC and mainboard a chance to update the UPD */ -- cgit v1.2.3