From 0755ab98a5f0d6632a4fc856d8812f5e70983a13 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 12 Jul 2017 15:31:06 +0530 Subject: intel/fsp: Add and use new post codes for FSP phase indication New post codes are POST_FSP_MEMORY_EXIT POST_FSP_SILICON_EXIT This patch will make it more consistent to debug FSP hang and reset issues. Bug=none Branch=none TEST=Build and Boot on eve Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/20541 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/drivers/intel/fsp2_0/memory_init.c | 2 +- src/drivers/intel/fsp2_0/silicon_init.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/drivers/intel/fsp2_0') diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 43888c1bad..b08ee1e768 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -361,7 +361,7 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); - post_code(POST_FSP_MEMORY_INIT); + post_code(POST_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); fsp_debug_after_memory_init(status); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 9f0bf7c892..bda88d11ca 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -49,7 +49,7 @@ static void do_silicon_init(struct fsp_header *hdr) post_code(POST_FSP_SILICON_INIT); status = silicon_init(&upd); timestamp_add_now(TS_FSP_SILICON_INIT_END); - post_code(POST_FSP_SILICON_INIT); + post_code(POST_FSP_SILICON_EXIT); fsp_debug_after_silicon_init(status); -- cgit v1.2.3