From e0165fbc944521171cd2776be4d3f655712079d2 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 9 Jan 2021 13:30:57 +0200 Subject: stage_cache: Add resume_from_stage_cache() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Factor out the condition when an attempt to load stage from cache can be tried. Change-Id: I936f07bed6fc82f46118d217f1fd233e2e041405 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/50000 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/drivers/intel/fsp2_0/silicon_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/drivers/intel/fsp2_0/silicon_init.c') diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index a4ffbda4cc..08494603f5 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -205,7 +205,7 @@ void fsps_load(bool s3wake) if (load_done) return; - if (s3wake && !CONFIG(NO_STAGE_CACHE)) { + if (resume_from_stage_cache()) { printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n"); stage_cache_load_stage(STAGE_REFCODE, fsps); if (fsp_validate_component(&fsps_hdr, prog_rdev(fsps)) != CB_SUCCESS) -- cgit v1.2.3