From cc93c6e47480de06ce87705a93bc46d806cabbb3 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 9 Jan 2021 22:53:52 +0200 Subject: soc/amd,intel: Drop s3_resume parameter on FSP-S functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Felix Held --- src/drivers/intel/fsp2_0/include/fsp/api.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/drivers/intel/fsp2_0/include') diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 63018c58db..8561600714 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -33,7 +33,7 @@ enum fsp_notify_phase { /* Main FSP stages */ void fsp_memory_init(bool s3wake); -void fsp_silicon_init(bool s3wake); +void fsp_silicon_init(void); void fsp_temp_ram_exit(void); /* @@ -41,7 +41,7 @@ void fsp_temp_ram_exit(void); * separately from calling silicon init. It might be required in cases where * stage cache is no longer available by the point SoC calls into silicon init. */ -void fsps_load(bool s3wake); +void fsps_load(void); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); -- cgit v1.2.3