From 33d9c4ad7e9e8048e90858edd8e0212e23a0ac8e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 26 May 2020 18:26:54 +0530 Subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit • Based on FSP EAS v2.1 – Backward compatibility is retained. • Add multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API. • Add FspMultiPhaseSiInit() API • FSP_INFO_HEADER changes o Added FspMultiPhaseSiInitEntryOffset • Add FSPS_ARCH_UPD o Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. FSP 2.2 Specification: https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/41728 Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/include/fsp/api.h | 5 ++++- src/drivers/intel/fsp2_0/include/fsp/info_header.h | 5 +++++ src/drivers/intel/fsp2_0/include/fsp/upd.h | 18 ++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 12 ++++++++++++ 4 files changed, 39 insertions(+), 1 deletion(-) (limited to 'src/drivers/intel/fsp2_0/include/fsp') diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index c6c9179867..d2c556f916 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -47,7 +47,10 @@ void fsps_load(bool s3wake); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); - +/* Callbacks for SoC/Mainboard specific overrides */ +void platform_fsp_multi_phase_init_cb(uint32_t phase_index); +/* Check if SoC sets EnableMultiPhaseSiliconInit UPD */ +int soc_fsp_multi_phase_init_is_enable(void); /* * The following functions are used when FSP_PLATFORM_MEMORY_SETTINGS_VERSION * is employed allowing the mainboard and SoC to supply their own version diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 7755d2a2f9..f237a378f1 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -6,7 +6,11 @@ #include #define FSP_HDR_OFFSET 0x94 +#if CONFIG(PLATFORM_USES_FSP2_2) +#define FSP_HDR_LEN 0x4c +#else #define FSP_HDR_LEN 0x48 +#endif #define FSP_HDR_SIGNATURE "FSPH" #define FSP_HDR_ATTRIB_FSPT 1 #define FSP_HDR_ATTRIB_FSPM 2 @@ -26,6 +30,7 @@ struct fsp_header { size_t notify_phase_entry_offset; size_t memory_init_entry_offset; size_t silicon_init_entry_offset; + size_t multi_phase_si_init_entry_offset; char image_id[sizeof(uint64_t) + 1]; uint8_t revision; }; diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h index bcfee6c727..979cff3b91 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/upd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -54,4 +54,22 @@ struct FSPM_ARCH_UPD { uint8_t Reserved1[8]; } __packed; +struct FSPS_ARCH_UPD { + /// + /// Revision of the structure. For FSP v2.2 value is 1. + /// + uint8_t Revision; + uint8_t Reserved[3]; + /// + /// Length of the structure in bytes. The current value for this field is 32 + /// + uint32_t Length; + uint8_t Reserved1[4]; + /// + /// To enable multi-phase silicon initialization the bootloader must set non-zero value + /// + uint8_t EnableMultiPhaseSiliconInit; + uint8_t Reserved2[19]; +} __packed; + #endif /* _FSP2_0_UPD_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 29c393b09c..ad6a4b5260 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -21,6 +21,17 @@ struct fsp_notify_params { enum fsp_notify_phase phase; }; +enum fsp_multi_phase_action { + GET_NUMBER_OF_PHASES = 0, + EXECUTE_PHASE = 1 +}; + +struct fsp_multi_phase_params { + enum fsp_multi_phase_action multi_phase_action; + uint32_t phase_index; + void *multi_phase_param_ptr; +}; + struct hob_resource { uint8_t owner_guid[16]; uint32_t type; @@ -115,6 +126,7 @@ typedef asmlinkage uint32_t (*temp_ram_exit_fn)(void *param); typedef asmlinkage uint32_t (*fsp_memory_init_fn) (void *raminit_upd, void **hob_list); typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd); +typedef asmlinkage uint32_t (*fsp_multi_phase_si_init_fn)(struct fsp_multi_phase_params *); typedef asmlinkage uint32_t (*fsp_notify_fn)(struct fsp_notify_params *); #include -- cgit v1.2.3