From 0a5971c91bac57970e3f3229b8cda735a17b3a67 Mon Sep 17 00:00:00 2001 From: Brenton Dong Date: Tue, 18 Oct 2016 11:35:15 -0700 Subject: drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for Cache-As-Ram initialization and teardown. Add fsp2_0 driver support for TempRamInit & TempRamExit APIs. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2 Signed-off-by: Brenton Dong Reviewed-on: https://review.coreboot.org/17062 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/drivers/intel/fsp2_0/include/fsp/info_header.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/drivers/intel/fsp2_0/include/fsp/info_header.h') diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 6351b32e63..c84c33ee8d 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -34,6 +34,8 @@ struct fsp_header { uint16_t component_attribute; size_t cfg_region_offset; size_t cfg_region_size; + size_t temp_ram_init_entry; + size_t temp_ram_exit_entry; size_t notify_phase_entry_offset; size_t memory_init_entry_offset; size_t silicon_init_entry_offset; -- cgit v1.2.3