From f4b20af9d716ff57d78d5d576e2990903bd70842 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 20 Feb 2017 13:33:32 -0800 Subject: drivers/intel/{fsp1_1,fsp2_0}: Provide separate function for fsp load Add a function to allow FSP component loading separately from silicon initialization. This enables SoCs that might not have stage cache available during silicon initialization to load/save components from/to stage cache before it is relocated or destroyed. BUG=chrome-os-partner:63114 BRANCH=None TEST=Compiles successfully. Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/18413 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Aaron Durbin --- src/drivers/intel/fsp2_0/include/fsp/api.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/drivers/intel/fsp2_0/include/fsp/api.h') diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 3b4334d804..3532ad2ef8 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -42,6 +42,13 @@ void fsp_memory_init(bool s3wake); void fsp_silicon_init(bool s3wake); void fsp_temp_ram_exit(void); +/* + * Load FSP-S from stage cache or CBFS. This allows SoCs to load FSPS-S + * separately from calling silicon init. It might be required in cases where + * stage cache is no longer available by the point SoC calls into silicon init. + */ +void fsps_load(bool s3wake); + /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); -- cgit v1.2.3