From 1e162bf8bd74e8dcd0b164b627e1d536c7dbd5f5 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 6 May 2016 09:20:35 -0700 Subject: lib/prog_loaders: Allow platforms to skip stage cache Before multi-CBFS support was added, x86 platforms cached their ramstage in TSEG so that it could be re-used on the resume path. However, more resources/assets are being put in cbfs that are utilized during ramstage. Just caching ramstage does not mean that correct cbfs region is used for all the data. Thus, provide an option to allow platforms to skip caching any component for resume. Change-Id: I0e957a6b859cc7d700aaff67209a17c6558be5de Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/14636 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/ramstage.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/drivers/intel/fsp1_1') diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 834f148071..6e2de29cea 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -158,6 +158,11 @@ static void fsp_cache_save(struct prog *fsp) if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP)) smm_memory_map(); + if (IS_ENABLED(CONFIG_NO_STAGE_CACHE)) + return; + + printk(BIOS_DEBUG, "FSP: Saving binary in cache\n"); + if (prog_entry(fsp) == NULL) { printk(BIOS_ERR, "ERROR: No FSP to save in cache.\n"); return; @@ -186,12 +191,11 @@ void intel_silicon_init(void) struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); int is_s3_wakeup = acpi_is_wakeup_s3(); - if (is_s3_wakeup) { + if (is_s3_wakeup && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); stage_cache_load_stage(STAGE_REFCODE, &fsp); } else { fsp_find_and_relocate(&fsp); - printk(BIOS_DEBUG, "FSP: Saving binary in cache\n"); fsp_cache_save(&fsp); } -- cgit v1.2.3