From d8e34b2c44605d2eb6ed1a955148ac24b9d0cd2e Mon Sep 17 00:00:00 2001 From: Teo Boon Tiong Date: Wed, 28 Dec 2016 18:56:26 +0800 Subject: driver/intel/fsp1_1: Fix boot failure for non-verstage case Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage and romstage will not be started at all. The solution is move out romstage_after_verstage.S from fsp1.1 driver to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the build and boot issue with this change. Besides that, rename the romstage_after_verstage to romstage_c_entry in more appropriate naming convention after this fix. Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0), romstage can be started successfully. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong Reviewed-on: https://review.coreboot.org/17976 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/romstage_after_verstage.S | 38 ---------------------- 1 file changed, 38 deletions(-) delete mode 100644 src/drivers/intel/fsp1_1/romstage_after_verstage.S (limited to 'src/drivers/intel/fsp1_1/romstage_after_verstage.S') diff --git a/src/drivers/intel/fsp1_1/romstage_after_verstage.S b/src/drivers/intel/fsp1_1/romstage_after_verstage.S deleted file mode 100644 index 2a3372f905..0000000000 --- a/src/drivers/intel/fsp1_1/romstage_after_verstage.S +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ - -.text -.global car_stage_entry -car_stage_entry: - call romstage_after_verstage - #include "after_raminit.S" - - movb $0x69, %ah - jmp .Lhlt - -.Lhlt: - xchg %al, %ah -#if IS_ENABLED(CONFIG_POST_IO) - outb %al, $CONFIG_POST_IO_PORT -#else - post_code(POST_DEAD_CODE) -#endif - movl $LHLT_DELAY, %ecx -.Lhlt_Delay: - outb %al, $0xED - loop .Lhlt_Delay - jmp .Lhlt -- cgit v1.2.3