From 66318aad07e6810065bc0668f4a1f34b7cb77687 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.h@gmx.de>
Date: Sat, 4 May 2019 16:59:20 +0200
Subject: intel/fsp1_1: Move MRC cache pointers into `romstage_params`

These are part of a common concept and not SoC specific.

Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
---
 src/drivers/intel/fsp1_1/include/fsp/romstage.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src/drivers/intel/fsp1_1/include')

diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index d608484999..4e95dadadf 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -18,6 +18,7 @@
 #ifndef _COMMON_ROMSTAGE_H_
 #define _COMMON_ROMSTAGE_H_
 
+#include <stddef.h>
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <memory_info.h>
@@ -32,6 +33,15 @@ struct romstage_params {
 	struct chipset_power_state *power_state;
 	struct pei_data *pei_data;
 	void *chipset_context;
+
+	/* Fast boot and S3 resume MRC data */
+	size_t saved_data_size;
+	const void *saved_data;
+	bool disable_saved_data;
+
+	/* New save data from MRC */
+	size_t data_to_save_size;
+	const void *data_to_save;
 };
 
 /*
-- 
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