From a887492e1e51849b75c7bb0d67430be4b1074493 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Wed, 26 Aug 2015 14:58:29 -0700 Subject: FSP: Pass FSP image base address to find_fsp Add a parameter to find_fsp which is the image base address. Adjust the fake stack in cache_as_ram.inc to pass in the read-only FSP image base address. In fsp_notify, pass in the read-only FSP image base address when the FSP header pointer is NULL. In find_fsp, validate the FSP binary image starting from the specified image base address. BRANCH=none BUG=None TEST=Build and run on Skylake Change-Id: Iac43c8aac8491390479af551765b514ca919928a Signed-off-by: Patrick Georgi Original-Commit-Id: 592dae53f3b32694190cc5cb0fa6ca94df68aa95 Original-Change-Id: I7d6a415458a81f3b6bcdcfc9a90eceb2ac22144e Original-Signed-off-by: Lee Leahy Original-Reviewed-on: https://chromium-review.googlesource.com/295593 Original-Commit-Ready: Leroy P Leahy Original-Tested-by: Leroy P Leahy Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/drivers/intel/fsp1_1/cache_as_ram.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/drivers/intel/fsp1_1/cache_as_ram.inc') diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 6af30ce5e5..d4df67b6ed 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -342,6 +342,7 @@ halt3: .align 4 fake_fsp_stack: .long find_fsp_ret + .long CONFIG_FSP_LOC /* FSP base address */ CAR_init_params: .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ -- cgit v1.2.3