From 7522a8fe0f7ef91bb3e66d3df1a2786bd4744f9b Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 20 Nov 2020 16:47:38 +0200 Subject: arch/x86: Move prologue to .init section MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For arch/x86 the realmode part has to be located within the same 64 KiB as the reset vector. Some older intel platforms also require 4 KiB alignment for _start16bit. To enforce the above, and to separate required parts of .text without matching *(.text.*) rules in linker scripts, tag the pre-C environment assembly code with section .init directive. Description of .init section for ELF: This section holds executable instructions that contribute to the process initialization code. When a program starts to run, the system arranges to execute the code in this section before calling the main program entry point (called main for C programs). Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/cache_as_ram.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/drivers/intel/fsp1_1/cache_as_ram.S') diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index f1cfff771c..e20d5277ed 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -14,6 +14,8 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ +.section .init, "ax", @progbits + .global bootblock_pre_c_entry bootblock_pre_c_entry: /* -- cgit v1.2.3