From 2524be4aff63e01637d28d6866fa23a513a3b8b1 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 29 Oct 2015 10:43:21 -0500 Subject: fsp1_1: pass ROM_SIZE to FSP for cacheable RO region As vboot verification works on regions outside of CBFS pass the entire ROM_SIZE to FSP for creating a cacheable RO region. Additionally remove the CACHE_ROM_SIZE_OVERRIDE as it doesn't work with non-power of 2 CBFS_SIZE. In practice the entire ROM should be attempted to be cached. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados w/ a 3MiB CBFS_SIZE. Change-Id: I61404c626ab2bcfd039d6eb3c01d9c13a0928446 Signed-off-by: Patrick Georgi Original-Commit-Id: 92568c630c48446b1ad9d4f22056f22e0679970c Original-Change-Id: I032e4d615d2b68d3a2e597555eb1b5034a74bf0a Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/309770 Original-Reviewed-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/12260 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/drivers/intel/fsp1_1/Kconfig | 9 --------- 1 file changed, 9 deletions(-) (limited to 'src/drivers/intel/fsp1_1/Kconfig') diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 5936f60065..4ae372746e 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -80,15 +80,6 @@ config FSP_LOC endif #HAVE_FSP_BIN -config CACHE_ROM_SIZE_OVERRIDE - hex "Cache ROM Size" - default CBFS_SIZE - help - This is the size of the cachable area that is passed into the FSP in - the early initialization. Typically this should be the size of the - CBFS area, but the size must be a power of 2 whereas the CBFS size - does not have this limitation. - config DISPLAY_FAST_BOOT_DATA bool "Display fast boot data" default n -- cgit v1.2.3