From e0c2c06ba17278e15ff805cbf75a6d5fc5ad474b Mon Sep 17 00:00:00 2001 From: Victor Ding Date: Thu, 18 Feb 2021 07:25:08 +0000 Subject: drivers/generic/bayhub_lv2: remove unnecessary configs coreboot sets up CLK_PM, ASPM, and L1ss automatically based on related bits in "Link Capability Register" and "L1 PM Substates Capabilities Register". coreboot overrides these configs even if the driver sets them. Therefore, setting up CLK_PM, ASPM, and L1ss in the driver is redundant and useless. BUG=b:177955523 BRANCH=zork TEST="lspci -vvvv" prints are identical with and without this patch; LV2_LINK_CTRL(0x90) is 0x00110102 with and without this patch. Signed-off-by: Victor Ding Change-Id: I17c19f4271da426ac2b926b948378dc88131e95a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50871 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Kangheui Won Reviewed-by: Angel Pons --- src/drivers/generic/bayhub_lv2/lv2.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'src/drivers/generic/bayhub_lv2/lv2.c') diff --git a/src/drivers/generic/bayhub_lv2/lv2.c b/src/drivers/generic/bayhub_lv2/lv2.c index 814cfb69c9..90e1e5d105 100644 --- a/src/drivers/generic/bayhub_lv2/lv2.c +++ b/src/drivers/generic/bayhub_lv2/lv2.c @@ -28,21 +28,15 @@ static void lv2_enable(struct device *dev) pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER); pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE); pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING); - pci_update_config32(dev, LV2_PCR_HEX_248, LV2_L1_SUBSTATE_SETTING_MASK, - LV2_L1_SUBSTATE_SETTING); pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK, LV2_L1_SUBSTATE_OPTIMISE); - pci_or_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_CLKREQ); pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW); pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK, LV2_DRIVER_STRENGTH); pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK, LV2_RESET_DMA_DISABLE); - pci_update_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_L1_L0_MASK, - LV2_LINK_CTRL_L1_ENABLE); pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON); - printk(BIOS_INFO, "BayHub LV2: Power-saving enabled (link_ctrl=%#x)\n", - pci_read_config32(dev, LV2_LINK_CTRL)); + printk(BIOS_INFO, "BayHub LV2: Power-saving enabled\n"); } static struct device_operations lv2_ops = { -- cgit v1.2.3