From 328ff7dee02e74d0d4e4107fd58810d0228203b8 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Mon, 27 Aug 2018 11:44:46 +0800 Subject: google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHz Bayhub eMMC controller default runs SD base 50MHz at the first power on. After boot into OS, mmc kernel driver will config controller to HS200/208MHz and send MMC CMD21 (tuning block). But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear after system warm reset. So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge. It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) to fail to load kernel and trap in 0x5B error (No bootable kernel found on disk). BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/28353 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/drivers/generic/bayhub/bh720.c | 4 ++-- src/drivers/generic/bayhub/bh720.h | 11 +++++++++-- 2 files changed, 11 insertions(+), 4 deletions(-) (limited to 'src/drivers/generic/bayhub') diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index b689b679d0..044168366b 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -23,7 +23,7 @@ #include "chip.h" #include "bh720.h" -__attribute__((weak)) void bh720_driving_strength(struct device *dev) +__attribute__((weak)) void board_bh720(struct device *dev) { } @@ -55,7 +55,7 @@ static void bh720_init(struct device *dev) pci_read_config32(dev, BH720_LINK_CTRL)); } - bh720_driving_strength(dev); + board_bh720(dev); } static struct pci_operations pci_ops = { diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h index b6fd2738cd..3a4b3b6f69 100644 --- a/src/drivers/generic/bayhub/bh720.h +++ b/src/drivers/generic/bayhub/bh720.h @@ -35,13 +35,20 @@ enum { BH720_MEM_RW_DATA = 0x200, BH720_MEM_RW_ADR = 0x204, + BH720_MEM_RW_READ = BIT(30), + BH720_MEM_RW_WRITE = BIT(31), BH720_MEM_ACCESS_EN = 0x208, - BH720_PCR = 0x304, + BH720_PCR_DrvStrength_PLL = 0x304, BH720_PCR_DATA_CMD_DRV_MAX = 7, BH720_PCR_CLK_DRV_MAX = 7, + BH720_PCR_EMMC_SETTING = 0x308, + BH720_PCR_EMMC_SETTING_1_8V = BIT(4), BH720_RTD3_L1 = 0x3e0, BH720_RTD3_L1_DISABLE_L1 = BIT(28), + + BH720_PCR_CSR = 0x3e4, + BH720_PCR_CSR_EMMC_MODE_SEL = BIT(22), }; -void bh720_driving_strength(struct device *dev); +void board_bh720(struct device *dev); -- cgit v1.2.3