From ba894be382c1a0365c435d5be2b54422731d66c8 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 25 Feb 2016 23:20:14 -0600 Subject: During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26 Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/13807 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Stefan Reinauer --- src/drivers/aspeed/common/ast_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/drivers/aspeed') diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 071e49caf2..264ef9d42d 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -232,7 +232,7 @@ static int ast_get_dram_info(struct drm_device *dev) data = ast_read32(ast, 0x10004); - if (data & 0x400) + if (data & 0x40) ast->dram_bus_width = 16; else ast->dram_bus_width = 32; -- cgit v1.2.3