From 04cf449e7727627969dadaf1aec829c429460ced Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 17:38:09 -0500 Subject: drivers/aspeed: Add native text mode VGA support for the AST2050 Change-Id: I37763a59d2546cd0c0e57b31fdb7aa77c2c50bee Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/11937 Reviewed-by: Peter Stuge Tested-by: build bot (Jenkins) --- src/drivers/aspeed/common/aspeed_coreboot.h | 210 ++++++++++++++++++++++++++++ 1 file changed, 210 insertions(+) create mode 100644 src/drivers/aspeed/common/aspeed_coreboot.h (limited to 'src/drivers/aspeed/common/aspeed_coreboot.h') diff --git a/src/drivers/aspeed/common/aspeed_coreboot.h b/src/drivers/aspeed/common/aspeed_coreboot.h new file mode 100644 index 0000000000..1331bb2d89 --- /dev/null +++ b/src/drivers/aspeed/common/aspeed_coreboot.h @@ -0,0 +1,210 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson , Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASPEED_COREBOOT_ +#define _ASPEED_COREBOOT_ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* coreboot <--> kernel code interface */ +#define __iomem +typedef u64 phys_addr_t; +#define pci_dev device + +#define SZ_16M 0x01000000 + +#define min_t(type, x, y) ({ \ + type __min1 = (x); \ + type __min2 = (y); \ + __min1 < __min2 ? __min1 : __min2; }) + +#define dev_info(dev, format, arg...) printk(BIOS_INFO, "%s: " format, __func__, ##arg) +#define dev_dbg(dev, format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg) +#define dev_err(dev, format, arg...) printk(BIOS_ERR, "%s: " format, __func__, ##arg) + +#define pr_info(format, arg...) printk(BIOS_INFO, "%s: " format, __func__, ##arg) +#define pr_debug(format, arg...) printk(BIOS_INFO, "%s: " format, __func__, ##arg) +#define pr_err(format, arg...) printk(BIOS_ERR, "%s: " format, __func__, ##arg) + +#define DRM_INFO pr_info + +#define GFP_KERNEL 0 +#define GFP_ATOMIC 1 +#define kfree(address) free(address) + +#define EIO 5 +#define ENOMEM 12 + +struct firmware { + size_t size; + const u8 *data; + struct page **pages; + + /* firmware loader private fields */ + void *priv; +}; + +struct drm_device { + struct pci_dev *pdev; + void *dev_private; +}; + +static inline void *kzalloc(size_t size, int flags) { + void* ptr = malloc(size); + memset(ptr, 0, size); + return ptr; +} + +static inline void writel(u32 val, volatile void *addr) { + *(u32*)addr = val; +} + +static inline u32 readl(const volatile void *addr) { + return *(u32*)addr; +} + +static inline void writew(u16 val, volatile void *addr) { + *(u16*)addr = val; +} + +static inline u16 readw(const volatile void *addr) { + return *(u16*)addr; +} + +static inline void writeb(u8 val, volatile void *addr) { + *(u8*)addr = val; +} + +static inline u8 readb(const volatile void *addr) { + return *(u8*)addr; +} + +static inline int pci_read_config_dword(struct pci_dev *dev, int where, + u32 *val) +{ + *val = pci_read_config32(dev, where); + return 0; +} + +static inline int pci_write_config_dword(struct pci_dev *dev, int where, + u32 val) +{ + pci_write_config32(dev, where, val); + return 0; +} + +static inline int pci_read_config_byte(struct pci_dev *dev, int where, + u8 *val) +{ + *val = pci_read_config8(dev, where); + return 0; +} + +static inline struct resource* resource_at_bar(struct pci_dev *dev, u8 bar) { + struct resource *res = dev->resource_list; + int i; + for (i = 0; i < bar; i++) { + res = res->next; + if (res == NULL) + return NULL; + } + + return res; +} + +static inline resource_t pci_resource_len(struct pci_dev *dev, u8 bar) { + struct resource *res = resource_at_bar(dev, bar); + if (res) + return res->size; + else + return 0; +} + +static inline resource_t pci_resource_start(struct pci_dev *dev, u8 bar) { + struct resource *res = resource_at_bar(dev, bar); + if (res) + return res->base; + else + return 0; +} + +static inline unsigned int ioread32(void __iomem *p) { + return readl(p); +} + +static inline void iowrite32(u32 val, void __iomem *p) { + writel(val, p); +} + +static inline unsigned int ioread16(void __iomem *p) { + return readw(p); +} + +static inline void iowrite16(u16 val, void __iomem *p) { + writew(val, p); +} + +static inline unsigned int ioread8(void __iomem *p) { + return readb(p); +} + +static inline void iowrite8(u8 val, void __iomem *p) { + writeb(val, p); +} + +static inline unsigned int ioread_cbio32(void __iomem *p) { + return inl((uint16_t)((intptr_t)p)); +} + +static inline void iowrite_cbio32(u32 val, void __iomem *p) { + outl(val, (uint16_t)((intptr_t)p)); +} + +static inline unsigned int ioread_cbio16(void __iomem *p) { + return inw((uint16_t)((intptr_t)p)); +} + +static inline void iowrite_cbio16(u16 val, void __iomem *p) { + outw(val, (uint16_t)((intptr_t)p)); +} + +static inline unsigned int ioread_cbio8(void __iomem *p) { + return inb((uint16_t)((intptr_t)p)); +} + +static inline void iowrite_cbio8(u8 val, void __iomem *p) { + outb(val, (uint16_t)((intptr_t)p)); +} + +static inline void msleep(unsigned int msecs) { + udelay(msecs * 1000); +} + +#endif -- cgit v1.2.3