From 48ae111ca80e5d35e2fa25fe39cf01bb2fc6e087 Mon Sep 17 00:00:00 2001 From: Xin Ji Date: Fri, 3 Sep 2021 11:11:44 +0800 Subject: drivers/analogix/anx7625: prevent video clock jitter on IVO panels The MIPI source video data has a large variation (e.g. 59Hz ~ 61Hz), anx7625 defines K ratio for matching MIPI input video clock and DP output video clock. A bigger k value can match a bigger video data variation. IVO panel has smaller variation than DP CTS spec, so decrease k value to 0x3b. BUG=b:194659777 BRANCH=none TEST=Display is normal on Asurada Change-Id: If3a09811999babda45e9a9a559dd447920109204 Signed-off-by: Xin Ji Reviewed-on: https://review.coreboot.org/c/coreboot/+/57439 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Hung-Te Lin --- src/drivers/analogix/anx7625/anx7625.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'src/drivers/analogix/anx7625/anx7625.c') diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index e37e047bbd..11e9ed1796 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -381,7 +381,7 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt) ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PLL_N_NUM_7_0, (n & 0xff)); /* diff */ - ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, 0x3d); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, dt->k_val); ret |= anx7625_odfc_config(bus, post_divider - 1); @@ -804,6 +804,20 @@ static void anx7625_parse_edid(const struct edid *edid, dt->vback_porch = (edid->mode.vbl - edid->mode.vso - edid->mode.vspw - edid->mode.vborder); + /* + * The k_val is a ratio to match MIPI input and DP output video clocks. + * Most panels can follow the default value (0x3d). + * IVO panels have smaller variation than DP CTS spec and need smaller + * k_val (0x3b). + */ + if (!strncmp(edid->manufacturer_name, "IVO", 3)) { + dt->k_val = 0x3b; + ANXINFO("detected IVO panel, use k value 0x3b\n"); + } else { + dt->k_val = 0x3d; + ANXINFO("set default k value to 0x3d for panel\n"); + } + ANXINFO("pixelclock(%d).\n" " hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n" " vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", -- cgit v1.2.3