From bf3f94dbb2832e43805c7533d6b5f8714b7398ef Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 31 Dec 2022 16:31:01 -0700 Subject: drivers/amd: Update to use defined post codes Signed-off-by: Martin Roth Change-Id: I2d5700534c07e89b3908a2e6b827db919a48795d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71591 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Fred Reitberger --- src/drivers/amd/agesa/cache_as_ram.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/drivers/amd') diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 0d678d1889..e3420397b1 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -12,6 +12,7 @@ #include #include +#include .section .init @@ -30,7 +31,7 @@ _cache_as_ram_setup: */ bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY) AMD_ENABLE_STACK @@ -56,7 +57,7 @@ bootblock_pre_c_entry: movd %mm1, %eax pushl %eax /* tsc[31:0] */ - post_code(0xa2) + post_code(POST_BOOTBLOCK_PRE_C_DONE) call bootblock_c_entry -- cgit v1.2.3