From 33d0fb8d346512e1b6819fa70cb17212ea014336 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Fri, 29 Nov 2019 06:38:46 +0200
Subject: AGESA,binaryPI: Add compatibility wrapper for romstage entry
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This simplifies transition and reviews towards C environment
bootblock by allowing single cache_as_ram.S file to be used.

Change-Id: I231972982e5ca6d0c08437693edf926b0eaf9ee1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37352
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/amd/agesa/cache_as_ram.S | 25 +++++++++++--------------
 src/drivers/amd/agesa/romstage.c     | 19 ++++++++++++++++---
 2 files changed, 27 insertions(+), 17 deletions(-)

(limited to 'src/drivers/amd')

diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index e86830f5f7..4417e64595 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -30,9 +30,6 @@
 
 _cache_as_ram_setup:
 
-	/* Preserve BIST. */
-	movd	%eax, %mm0
-
 	post_code(0xa0)
 
 	AMD_ENABLE_STACK
@@ -50,16 +47,16 @@ _cache_as_ram_setup:
 
 	mov	$_ecar_stack, %esp
 
-	/* Align the stack. */
-	and	$0xFFFFFFF0, %esp
+	/* Align the stack and keep aligned for call to bootblock_c_entry() */
+	and	$0xfffffff0, %esp
+	sub	$8, %esp
+
+	pushl	$0		/* tsc[63:32] */
+	pushl	$0		/* tsc[31:0] */
+
+	post_code(0xa2)
 
-	/* Must maintain 16-byte stack alignment here. */
-	pushl	$0x0
-	pushl	$0x0
-	pushl	$0x0
-	movd	%mm0, %eax		/* bist */
-	pushl	%eax
-	call	romstage_main
+	call	bootblock_c_entry
 
 	/* Never reached. */
 
@@ -69,9 +66,9 @@ stop:
 	jmp	stop
 
 ap_entry:
-	/* Align the stack for call to ap_romstage_main() */
+	/* Align the stack for call to ap_bootblock_c_entry() */
 	and	$0xfffffff0, %esp
-	call	ap_romstage_main
+	call	ap_bootblock_c_entry
 
 	/* Never reached. */
 	jmp	stop
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 571397fdb3..48a81c57df 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -14,8 +14,8 @@
 #include <arch/acpi.h>
 #include <arch/cpu.h>
 #include <arch/romstage.h>
+#include <bootblock_common.h>
 #include <cbmem.h>
-#include <cpu/amd/car.h>
 #include <console/console.h>
 #include <halt.h>
 #include <program_loading.h>
@@ -39,7 +39,7 @@ static void fill_sysinfo(struct sysinfo *cb)
 	agesa_set_interface(cb);
 }
 
-asmlinkage void romstage_main(unsigned long bist)
+static void romstage_main(void)
 {
 	struct postcar_frame pcf;
 	struct sysinfo romstage_state;
@@ -99,7 +99,7 @@ asmlinkage void romstage_main(unsigned long bist)
 	/* We do not return. */
 }
 
-asmlinkage void ap_romstage_main(void)
+static void ap_romstage_main(void)
 {
 	struct sysinfo romstage_state;
 	struct sysinfo *cb = &romstage_state;
@@ -116,3 +116,16 @@ asmlinkage void ap_romstage_main(void)
 	/* Not reached. */
 	halt();
 }
+
+/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK
+ * keeping changes in cache_as_ram.S easy to manage.
+ */
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+	romstage_main();
+}
+
+asmlinkage void ap_bootblock_c_entry(void)
+{
+	ap_romstage_main();
+}
-- 
cgit v1.2.3