From 9266ce90c6cf6962f612b59a173149eca4e1538f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 25 Nov 2019 18:21:05 +0200 Subject: AGESA,binaryPI: Remove early_all_cores() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was implemented to make sure it gets called before attempting any PCI MMIO access. Now that we have one central romstage_main() implementation this extra precaution is no longer useful. Change-Id: I09b24da827e00d7a9ba0a51d5eef36f174b893a6 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37203 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Michał Żygowski --- src/drivers/amd/agesa/cache_as_ram.S | 2 -- src/drivers/amd/agesa/romstage.c | 12 +++--------- 2 files changed, 3 insertions(+), 11 deletions(-) (limited to 'src/drivers/amd/agesa') diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 3f1358a2f8..e3e5735c3b 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -94,8 +94,6 @@ _cache_as_ram_setup: #endif - call early_all_cores - /* Must maintain 16-byte stack alignment here. */ pushl $0x0 pushl $0x0 diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 72aac3eedd..0ecfeb2bb6 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -27,15 +27,6 @@ #include #include -#if !CONFIG(POSTCAR_STAGE) -#error "Only POSTCAR_STAGE is supported." -#endif - -void asmlinkage early_all_cores(void) -{ - amd_initmmio(); -} - void __weak platform_once(struct sysinfo *cb) { board_BeforeAgesa(cb); @@ -57,6 +48,9 @@ void *asmlinkage romstage_main(unsigned long bist) u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); int cbmem_initted = 0; + /* Enable PCI MMIO configuration. */ + amd_initmmio(); + fill_sysinfo(cb); if ((initial_apic_id == 0) && boot_cpu()) { -- cgit v1.2.3