From 1e67adbc73e30be098ce163e3d27a7a7ecf68ae0 Mon Sep 17 00:00:00 2001 From: Yuchen He Date: Tue, 25 Jul 2023 21:28:36 +0200 Subject: src/*/post_code.h: Change post code prefix to POSTCODE The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. header="src/soc/amd/common/block/include/amdblocks/post_codes.h \ src/include/cpu/intel/post_codes.h \ src/soc/intel/common/block/include/intelblocks/post_codes.h" array=`grep -r "#define POST_" $header | \ tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2` for str in $array; do splitstr=`echo $str | cut -d '_' -f2-` grep -r $str src | cut -d ':' -f 1 | \ xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g" done Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: Yuchen He Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/drivers/amd/agesa/cache_as_ram.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/drivers/amd/agesa') diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 9fd1a0aba2..5e77263c97 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -31,7 +31,7 @@ _cache_as_ram_setup: */ bootblock_pre_c_entry: - post_code(POST_BOOTBLOCK_PRE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY) AMD_ENABLE_STACK @@ -57,7 +57,7 @@ bootblock_pre_c_entry: movd %mm1, %eax pushl %eax /* tsc[31:0] */ - post_code(POST_BOOTBLOCK_PRE_C_DONE) + post_code(POSTCODE_BOOTBLOCK_PRE_C_DONE) call bootblock_c_entry -- cgit v1.2.3