From 607cdf62b665230a943a271042bf9c3bf9803cab Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 26 Apr 2010 12:08:51 +0000 Subject: fix a bug in pcibios check. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/devices/oprom/x86_asm.S | 16 +++++++------- src/devices/oprom/x86_interrupts.c | 43 ++++++++++++-------------------------- 2 files changed, 21 insertions(+), 38 deletions(-) (limited to 'src/devices/oprom') diff --git a/src/devices/oprom/x86_asm.S b/src/devices/oprom/x86_asm.S index 03c6994046..724fe02c0d 100644 --- a/src/devices/oprom/x86_asm.S +++ b/src/devices/oprom/x86_asm.S @@ -49,8 +49,8 @@ __realmode_code: /* Realmode IDT pointer structure. */ .globl __realmode_idt __realmode_idt = RELOCATED(.) - .word 1023 /* 16-bit limit */ - .long 0 /* 24-bit base */ + .word 1023 /* 16 bit limit */ + .long 0 /* 24 bit base */ .word 0 /* Preserve old stack */ @@ -101,14 +101,14 @@ __run_optionrom = RELOCATED(.) 1: /* Setup a stack: Put the stack at the end of page zero. * That way we can easily share it between real and - * protected, since the 16-bit ESP at segment 0 will + * protected, since the 16 bit ESP at segment 0 will * work for any case. */ mov $0x0, %ax mov %ax, %ss movl $0x1000, %eax movl %eax, %esp - /* Load our 16 bit idt */ + /* Load 16 bit IDT */ xor %ax, %ax mov %ax, %ds lidt __realmode_idt @@ -119,9 +119,9 @@ __run_optionrom = RELOCATED(.) mov %ax, %gs mov $0x40, %ax mov %ax, %ds - mov %cx, %ax // restore ax /* ************************************ */ + mov %cx, %ax // restore ax // TODO this will not work for non-VGA option ROMs /* run VGA BIOS at 0xc000:0003 */ lcall $0xc000, $0x0003 @@ -201,7 +201,7 @@ __run_vsa = RELOCATED(.) 1: /* Setup a stack: Put the stack at the end of page zero. * That way we can easily share it between real and - * protected, since the 16-bit ESP at segment 0 will + * protected, since the 16 bit ESP at segment 0 will * work for any case. */ mov $0x0, %ax mov %ax, %ss @@ -415,12 +415,12 @@ __interrupt_handler_16bit = RELOCATED(.) mov $0x0, %ax mov %ax, %ss - /* Restore 16-bit IDT */ + /* Restore 16 bit IDT */ xor %ax, %ax mov %ax, %ds lidt __realmode_idt - /* Set up our segment registers to segment 0x0000 */ + /* Set up segment registers to segment 0x0000 */ mov %ax, %es mov %ax, %fs mov %ax, %gs diff --git a/src/devices/oprom/x86_interrupts.c b/src/devices/oprom/x86_interrupts.c index 95964f89f2..90156334dc 100644 --- a/src/devices/oprom/x86_interrupts.c +++ b/src/devices/oprom/x86_interrupts.c @@ -58,6 +58,11 @@ int int12_handler(struct eregs *regs) return 0; } +#define PCI_CONFIG_SPACE_TYPE1 (1 << 0) +#define PCI_CONFIG_SPACE_TYPE2 (1 << 1) +#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4) +#define PCI_SPECIAL_CYCLE_TYPE2 (1 << 5) + int int1a_handler(struct eregs *regs) { unsigned short func = (unsigned short)regs->eax; @@ -74,6 +79,11 @@ int int1a_handler(struct eregs *regs) switch (func) { case PCIBIOS_CHECK: regs->edx = 0x20494350; /* ' ICP' */ + regs->eax &= 0xffff0000; /* Clear AH / AL */ + regs->eax |= PCI_CONFIG_SPACE_TYPE1 | PCI_SPECIAL_CYCLE_TYPE1; + // last bus in the system. Hard code to 255 for now. + // dev_enumerate() does not seem to tell us (publically) + regs->ecx = 0xff; regs->edi = 0x00000000; /* protected mode entry */ retval = 0; break; @@ -114,7 +124,7 @@ int int1a_handler(struct eregs *regs) dev = dev_find_slot(bus, devfn); if (!dev) { printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn); - // idiots. the pcibios guys assumed you'd never pass a bad bus/devfn! + // Or are we supposed to return PCIBIOS_NODEV? regs->eax = PCIBIOS_BADREG; retval = -1; return retval; @@ -164,38 +174,12 @@ int int15_handler(struct eregs *regs) { int res = -1; - /* This int15 handler is VIA Tech. specific. Other chipsets need other + /* This int15 handler is Intel IGD. specific. Other chipsets need other * handlers. The right way to do this is to move this handler code into * the mainboard or northbridge code. + * TODO: completely move to mainboards / chipsets. */ switch (regs->eax & 0xffff) { - case 0x5f19: - break; - case 0x5f18: - regs->eax = 0x5f; - // MCLK = 133, 32M frame buffer, 256 M main memory - regs->ebx = 0x545; - regs->ecx = 0x060; - res = 0; - break; - case 0x5f00: - regs->eax = 0x8600; - break; - case 0x5f01: - regs->eax = 0x5f; - regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 - res = 0; - break; - case 0x5f02: - regs->eax = 0x5f; - regs->ebx = (regs->ebx & 0xffff0000) | 2; - regs->ecx = (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only - regs->edx = (regs->edx & 0xffff0000) | 0; // TV Layout - default - res = 0; - break; - case 0x5f0f: - regs->eax = 0x860f; - break; /* And now Intel IGD code */ #define BOOT_DISPLAY_DEFAULT 0 #define BOOT_DISPLAY_CRT (1 << 0) @@ -206,7 +190,6 @@ int int15_handler(struct eregs *regs) #define BOOT_DISPLAY_TV2 (1 << 5) #define BOOT_DISPLAY_EFP2 (1 << 6) #define BOOT_DISPLAY_LCD2 (1 << 7) - case 0x5f35: regs->eax = 0x5f; regs->ecx = BOOT_DISPLAY_DEFAULT; -- cgit v1.2.3