From c2ffe89f777dfd85308177e126b22f10ef5c2e0a Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 7 Mar 2021 00:29:20 +0100 Subject: pci_def.h: Introduce PCI_EXP_DEVCAP2 & PCI_EXP_DEVCTL2 proper Replace the existing, odd looking, unordered definitions used for LTR configuration with the usual names used by upstream libpci. TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes. Fixes: Code looked like UEFI copy-pasta. Header file was a mess. Change-Id: Icf666692e22730e1bdf4bcdada433b3219af568a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/51327 Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/device/pciexp_device.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/device') diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 3153e0eb37..0b7c649d93 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -140,9 +140,9 @@ static bool pciexp_is_ltr_supported(struct device *dev, unsigned int cap) { unsigned int val; - val = pci_read_config16(dev, cap + PCI_EXP_DEV_CAP2_OFFSET); + val = pci_read_config16(dev, cap + PCI_EXP_DEVCAP2); - if (val & LTR_MECHANISM_SUPPORT) + if (val & PCI_EXP_DEVCAP2_LTR) return true; return false; @@ -164,10 +164,10 @@ static void pciexp_configure_ltr(struct device *dev) return; } - cap += PCI_EXP_DEV_CTL_STS2_CAP_OFFSET; + cap += PCI_EXP_DEVCTL2; /* Enable LTR for device */ - pci_update_config32(dev, cap, ~LTR_MECHANISM_EN, LTR_MECHANISM_EN); + pci_update_config32(dev, cap, ~PCI_EXP_DEV2_LTR, PCI_EXP_DEV2_LTR); /* Configure Max Snoop Latency */ pciexp_config_max_latency(dev->bus->dev, dev); -- cgit v1.2.3