From 4c66daaadd885c7dcd7700764102208e713c7609 Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Tue, 31 Aug 2021 15:42:20 -0600 Subject: device/dram: Add addtional LPDDR4 speed grades Add additonal LPDDR4 speed grades. This is needed because the limited set has casued confusion when the reported speed did not match expectations. There does not seem to be a definitive list of LPDDR4 speed grades, so this list is derieved from JEDEC 209-4C and a survey of commonly used LPDDR4 speed grades. BUG=b:194184950 TEST=Boot, dmidecode -t 17 reports correct speed BRANCH=None Change-Id: Ie7706fd4ad5a7df68c07b8ca43261429ba140c61 Signed-off-by: Rob Barnes Reviewed-on: https://review.coreboot.org/c/coreboot/+/57294 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Nikolai Vyssotski --- src/device/dram/lpddr4.c | 44 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 37 insertions(+), 7 deletions(-) (limited to 'src/device/dram/lpddr4.c') diff --git a/src/device/dram/lpddr4.c b/src/device/dram/lpddr4.c index 990af9334e..3c686d0107 100644 --- a/src/device/dram/lpddr4.c +++ b/src/device/dram/lpddr4.c @@ -10,10 +10,15 @@ #include enum lpddr4_speed_grade { + LPDDR4_1333, LPDDR4_1600, + LPDDR4_1866, + LPDDR4_2133, LPDDR4_2400, + LPDDR4_2666, LPDDR4_3200, - LPDDR4_4266 + LPDDR4_3733, + LPDDR4_4266, }; struct lpddr4_speed_attr { @@ -23,7 +28,7 @@ struct lpddr4_speed_attr { }; /** - * LPDDR4 speed attributes derived from JEDEC 209-4C table 210 + * LPDDR4 speed attributes derived from JEDEC 209-4C and industry norms * * min_clock_mhz = Previous max_clock_mhz + 1 * max_clock_mhz = 1000/min_tCk_avg(ns) @@ -31,24 +36,49 @@ struct lpddr4_speed_attr { * May be slightly less than the actual max MT/s */ static const struct lpddr4_speed_attr lpddr4_speeds[] = { - [LPDDR4_1600] = { + [LPDDR4_1333] = { .min_clock_mhz = 10, + .max_clock_mhz = 667, + .reported_mts = 1333, + }, + [LPDDR4_1600] = { + .min_clock_mhz = 668, .max_clock_mhz = 800, .reported_mts = 1600 }, - [LPDDR4_2400] = { + [LPDDR4_1866] = { .min_clock_mhz = 801, + .max_clock_mhz = 934, + .reported_mts = 1866, + }, + [LPDDR4_2133] = { + .min_clock_mhz = 935, + .max_clock_mhz = 1067, + .reported_mts = 2133 + }, + [LPDDR4_2400] = { + .min_clock_mhz = 1068, .max_clock_mhz = 1200, .reported_mts = 2400 }, - [LPDDR4_3200] = { + [LPDDR4_2666] = { .min_clock_mhz = 1201, + .max_clock_mhz = 1333, + .reported_mts = 2666 + }, + [LPDDR4_3200] = { + .min_clock_mhz = 1334, .max_clock_mhz = 1600, .reported_mts = 3200 }, - [LPDDR4_4266] = { + [LPDDR4_3733] = { .min_clock_mhz = 1601, - .max_clock_mhz = 2137, + .max_clock_mhz = 1867, + .reported_mts = 3733 + }, + [LPDDR4_4266] = { + .min_clock_mhz = 1868, + .max_clock_mhz = 2134, .reported_mts = 4266 }, }; -- cgit v1.2.3