From ffcac3eb502bbe0acbb30d6fe804f00e07461a7a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 15:46:49 +0100 Subject: nb/amd/fam10: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: If36ef0749dbb661f731fb04829bd7e2202ebb422 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36962 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/cpu/amd/family_10h-family_15h/fidvid.c | 4 ++-- src/cpu/amd/family_10h-family_15h/init_cpus.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 57207a431a..d4dec2b1c0 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -505,7 +505,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, } /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ - #if CONFIG(SVI_HIGH_FREQ) + #if 0 if (cpuRev & AMD_FAM10_C3) { dword |= SVI_HIGH_FREQ_ON; } @@ -585,7 +585,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, if (cpuRev & AMD_DR_Bx ) { smaf001 = 0xA6; } else { - #if CONFIG(SVI_HIGH_FREQ) + #if 0 if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { smaf001 = 0xF6; } diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index c7ef86a5a1..ae04f2aace 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -576,7 +576,7 @@ static void start_node(u8 node) /* Enable routing table */ printk(BIOS_DEBUG, "Start node %02x", node); -#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) +#if 0 /* For FAM10 support, we need to set Dram base/limit for the new node */ pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x40, 3); -- cgit v1.2.3