From f6bbc603fadf4fdb6c9c86775739ff1b32ab5f1e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 26 Nov 2017 15:34:20 +0100 Subject: intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/22603 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Martin Roth --- src/cpu/x86/lapic/apic_timer.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 254bb07b11..ec2e71c39e 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -48,6 +48,7 @@ static int set_timer_fsb(void) int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 }; int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 }; + msr_t msr; get_fms(&c, cpuid_eax(1)); switch (c.x86) { @@ -74,16 +75,17 @@ static int set_timer_fsb(void) return 0; } case 0xf: /* Netburst */ + msr = rdmsr(MSR_EBC_FREQUENCY_ID); switch (c.x86_model) { case 0x2: car_set_var(g_timer_fsb, - f2x_fsb[(rdmsr(0x2c).lo >> 16) & 7]); + f2x_fsb[(msr.lo >> 16) & 7]); return 0; case 0x3: case 0x4: case 0x6: car_set_var(g_timer_fsb, - core2_fsb[(rdmsr(0x2c).lo >> 16) & 7]); + core2_fsb[(msr.lo >> 16) & 7]); return 0; } /* default: fallthrough */ default: -- cgit v1.2.3