From f0a13ceb639f7a7d5a6e84a2c89f3deab0de757a Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Sun, 8 Dec 2013 07:20:48 +0200
Subject: AMD boards: Fix includes for microcode updates
MIME-Version: 1.0
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No ROMCC involved, no need to include .c files in romstage.c.

Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4501
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
 src/cpu/amd/microcode/Makefile.inc                 |  1 +
 src/cpu/amd/microcode/microcode.c                  |  7 -------
 src/cpu/amd/model_10xxx/Makefile.inc               |  3 ++-
 src/cpu/amd/model_10xxx/init_cpus.c                |  3 +--
 src/cpu/amd/model_10xxx/update_microcode.c         | 10 +---------
 src/cpu/amd/model_fxx/model_fxx_update_microcode.c |  3 ---
 6 files changed, 5 insertions(+), 22 deletions(-)

(limited to 'src/cpu')

diff --git a/src/cpu/amd/microcode/Makefile.inc b/src/cpu/amd/microcode/Makefile.inc
index 6631019f38..48f1d0d136 100644
--- a/src/cpu/amd/microcode/Makefile.inc
+++ b/src/cpu/amd/microcode/Makefile.inc
@@ -1 +1,2 @@
 ramstage-y += microcode.c
+romstage-$(CONFIG_UPDATE_CPU_MICROCODE) += microcode.c
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 1e94daba08..46d814e0c9 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -17,17 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef __ROMCC__
 #include <stdint.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/microcode.h>
-#endif
-
-#ifndef __PRE_RAM__
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#endif
 
 struct microcode {
 	u32 date_code;
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index 81c565b621..c78f6403d8 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -1,3 +1,4 @@
 ramstage-y += model_10xxx_init.c
-ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c
 ramstage-y += processor_name.c
+
+romstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index eb047b8db2..3ebd7f2358 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -325,9 +325,8 @@ static u32 init_cpus(u32 cpu_init_detectedx)
 		 * This happens after HTinit.
 		 * The BSP runs this code in it's own path.
 		 */
-#if CONFIG_UPDATE_CPU_MICROCODE
 		update_microcode(cpuid_eax(1));
-#endif
+
 		cpuSetAMDMSR();
 
 #if CONFIG_SET_FIDVID
diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c
index cc08cdc546..95624e94c6 100644
--- a/src/cpu/amd/model_10xxx/update_microcode.c
+++ b/src/cpu/amd/model_10xxx/update_microcode.c
@@ -17,17 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-
-#ifndef __PRE_RAM__
+#include <stdint.h>
 #include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#endif
-
-#ifndef __ROMCC__
 #include <cpu/amd/microcode.h>
-#endif
 
 static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
 
diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
index f1747d98af..4a53feaa29 100644
--- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
+++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
@@ -20,9 +20,6 @@
  */
 
 #include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
 #include <cpu/amd/microcode.h>
 
 static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
-- 
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