From e751a101c08d540c59fc39def9681a0ee227d825 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Nov 2020 13:28:57 +0100 Subject: soc/intel/broadwell: Move romstage.c to Haswell Broadwell no longer has CPU code. Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46951 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/Makefile.inc | 2 ++ src/cpu/intel/haswell/romstage.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 src/cpu/intel/haswell/romstage.c (limited to 'src/cpu') diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 3c4db4f1c8..bfb501133c 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,4 +1,6 @@ ramstage-y += haswell_init.c + +romstage-y += romstage.c romstage-y += ../car/romstage.c ramstage-y += acpi.c diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c new file mode 100644 index 0000000000..3b11e93cab --- /dev/null +++ b/src/cpu/intel/haswell/romstage.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void set_max_freq(void) +{ + msr_t msr, perf_ctl, platform_info; + + /* Check for configurable TDP option */ + platform_info = rdmsr(MSR_PLATFORM_INFO); + + if ((platform_info.hi >> 1) & 3) { + /* Set to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + + perf_ctl.hi = 0; + wrmsr(IA32_PERF_CTL, perf_ctl); + + printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); +} -- cgit v1.2.3