From de01136484c58d13457ccf1e42fdb2310f3cbe65 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 17 Nov 2016 22:39:29 +0200 Subject: intel post-car: Increase stacktop alignment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align top of stack to 8 bytes, value documented as FSP1.1 requirement. Also fix some cases of uintptr_t casted to unsigned long. Change-Id: I5bbd100eeb673417da205a2c2c3410fef1af61f0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17461 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- src/cpu/intel/haswell/romstage.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index f823c55b0c..48920b3968 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -69,15 +69,13 @@ static inline u32 *stack_push(u32 *stack, u32 value) * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_romstage_stack_after_car(void) { - uintptr_t top_of_stack; int num_mtrrs; u32 *slot; u32 mtrr_mask_upper; u32 top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = romstage_ram_stack_top() & ~3; - slot = (void *)top_of_stack; + slot = (void *)romstage_ram_stack_top(); num_mtrrs = 0; /* The upper bits of the MTRR mask need to set according to the number -- cgit v1.2.3