From dc4820baed8ac592a5583ebdd97c8ed892a5b0b6 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 21 Jul 2016 19:51:01 +0300 Subject: intel car: Use MTRR WRPROT type for XIP cache MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit XIP cachelines contain the executable to run, we never want that to get modified. With the change such erronous writes are ignored and next cacheline miss will fetch from boot media (SPI / FWH flash). Change-Id: I52b62866b5658e103281ffa1a91e1c64262f3175 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15778 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/car/cache_as_ram_ht.inc | 2 +- src/cpu/intel/model_6ex/cache_as_ram.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index f9a2b3637a..0ec2a9d43d 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -310,7 +310,7 @@ no_msr_11e: */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax + orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 1f2445a2ab..b4c8d62b63 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -111,7 +111,7 @@ clear_mtrrs: */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax + orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx -- cgit v1.2.3