From cb70d836ed048b81ad8047e97c9758680cc2da2d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 11 Oct 2021 14:26:42 +0200 Subject: cpu/intel/haswell: Lock PKG_CST_CONFIG_CONTROL MSR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only. Change-Id: Ieb740aa94255cb3c23a56495c4b645d847637b7f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58222 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak --- src/cpu/intel/haswell/haswell_init.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu') diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 2c6384c4e3..90db95b8df 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -395,6 +395,7 @@ static void configure_c_states(void) msr.lo |= (1 << 27); // C3 Auto Undemotion Enable msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable + msr.lo |= (1 << 15); // Lock bits 15:0 msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection if (timed_mwait_capable) -- cgit v1.2.3