From bd56bf0dcff59d38066715438a9350f50136fcc3 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Thu, 8 Aug 2013 16:04:07 -0700 Subject: exynos5420: correct the PMS value for CPLL This patch matches the User Manual Table 7-2 about the PMS value for CPLL. This doesn't change the PLL frequency (before and after both make 666MHz) but this is the suggested PMSK values for obtaining 666. (Suggested as per user manual). This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/ Signed-off-by: David Hendricks Change-Id: Ia33e1971ab88da761000d443792560476514626b Reviewed-on: https://gerrit.chromium.org/gerrit/65281 Reviewed-by: Gabe Black Commit-Queue: David Hendricks Tested-by: David Hendricks Reviewed-on: http://review.coreboot.org/4460 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/samsung/exynos5420/clock_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 352163619c..07bf5d95c2 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -113,7 +113,7 @@ void system_clock_init(void) /* Set CPLL */ writel(CPLL_CON1_VAL, &clk->cpll_con1); - val = set_pll(0x6f, 0x2, 0x1); + val = set_pll(0xde, 0x4, 0x1); writel(val, &clk->cpll_con0); while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0) ; -- cgit v1.2.3