From b84c833bfd258f92fc7d24b2308537e41b7b8ce4 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 1 Dec 2016 10:48:43 +0200 Subject: intel/sandybridge: Use postcar_frame for MTRR setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adapt implementation from skylake. Change-Id: Ica3134a2261d3e84c714264cf75557322f9ef5db Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17673 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Aaron Durbin --- src/cpu/intel/model_206ax/cache_as_ram.inc | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index f0d49390ba..149cae6581 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -225,12 +225,29 @@ before_romstage: post_code(0x38) - /* Get number of MTRRs. */ + /* Clear all of the variable MTRRs. */ popl %ebx movl $MTRR_PHYS_BASE(0), %ecx + clr %eax + clr %edx + 1: testl %ebx, %ebx jz 1f + wrmsr /* Write MTRR base. */ + inc %ecx + wrmsr /* Write MTRR mask. */ + inc %ecx + dec %ebx + jmp 1b + +1: + /* Get number of MTRRs. */ + popl %ebx + movl $MTRR_PHYS_BASE(0), %ecx +2: + testl %ebx, %ebx + jz 2f /* Low 32 bits of MTRR base. */ popl %eax @@ -248,8 +265,9 @@ before_romstage: inc %ecx dec %ebx - jmp 1b -1: + jmp 2b +2: + post_code(0x39) /* And enable cache again after setting MTRRs. */ -- cgit v1.2.3