From ac00a0a7e2a4a7dccf4cde3f4d7550c07df216a2 Mon Sep 17 00:00:00 2001 From: Greg Watson Date: Sun, 7 Mar 2004 17:28:59 +0000 Subject: fix caching problem git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/ppc/mpc74xx/Config.lb | 3 ++- src/cpu/ppc/mpc74xx/cache.S | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 src/cpu/ppc/mpc74xx/cache.S (limited to 'src/cpu') diff --git a/src/cpu/ppc/mpc74xx/Config.lb b/src/cpu/ppc/mpc74xx/Config.lb index 3c74233845..6005d9855c 100644 --- a/src/cpu/ppc/mpc74xx/Config.lb +++ b/src/cpu/ppc/mpc74xx/Config.lb @@ -17,6 +17,7 @@ default DCACHE_RAM_SIZE=0x8000 initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc object clock.o +object cache.S initobject clock.o -initobject cache.o +initobject cache.S diff --git a/src/cpu/ppc/mpc74xx/cache.S b/src/cpu/ppc/mpc74xx/cache.S new file mode 100644 index 0000000000..237b178bdf --- /dev/null +++ b/src/cpu/ppc/mpc74xx/cache.S @@ -0,0 +1,23 @@ +#define ASM +#include "ppcreg.h" +#include + +#define NUM_CACHE_LINES 128*8 +#define L1_CACHE_LINE_SIZE 32 +#define cache_flush_buffer 0x1000 + +/* + * Flush data cache + * Do this by just reading lots of stuff into the cache. + */ +.globl flush_dcache +flush_dcache: + lis r3,cache_flush_buffer@h + ori r3,r3,cache_flush_buffer@l + li r4,NUM_CACHE_LINES + mtctr r4 +0: lwz r4,0(r3) + addi r3,r3,L1_CACHE_LINE_SIZE + bdnz 0b + blr + -- cgit v1.2.3