From 99f80422f68885d8c7a8489563815457e5c1bbfb Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 7 Aug 2015 23:58:28 -0500 Subject: cpu/amd/family_10h-family_15h: Configure NB register 2 Change-Id: I55cfc96a197514212b2a4c344d3513396ebc2ad4 Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/12032 Tested-by: Raptor Engineering Automated Test Stand Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index 901b8ce0a3..3fd0f4b3b4 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -604,6 +604,14 @@ static const struct { [5] DisPciCfgCpuMstAbtRsp = 1, [1] SyncFloodOnUsPwDataErr = 1 */ + /* NB Configuration 2 */ + { 3, 0x188, AMD_DR_GT_B0, AMD_PTYPE_ALL, + 0x00000010, 0x00000010 }, /* EnStpGntOnFlushMaskWakeup = 0x1 */ + + /* NB Configuration 2 */ + { 3, 0x188, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00000200, 0x00000200 }, /* DisL3HiPriFreeListAlloc = 0x1 */ + /* errata 346 - Fam10 C2, C3 * System software should set F3x188[22] to 1b. */ { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL, -- cgit v1.2.3