From 8d32b89fa4ea30aa57b578d79bc656c9e6545795 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 10 Jul 2012 13:24:29 -0700 Subject: Fix LAPIC timer on Ivy Bridge systems The LAPIC timer is running at BCLK (100MHz) on Sandy Bridge and Ivy Bridge systems. However, the current timer code assumed that the clock would run at 200MHz instead. This made all delays twice as long as needed. Change-Id: I41b1186daee11cfd9a25b3a9d5ebdeeb271293c7 Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/1330 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/cpu/x86/lapic/apic_timer.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu') diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 1fd0c60234..562c79c2e8 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -50,6 +50,7 @@ static int set_timer_fsb(void) timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ + case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ timer_fsb = 100; break; default: -- cgit v1.2.3