From 7f3741840c68679db36d359c9c96dad48af63536 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 15 Mar 2017 08:45:00 +0200 Subject: AGESA f14: Fix infinite loop MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix regression after commit: 22f32c7 cpu/amd/agesa: Unify init files Change-Id: I36fb7369084c68577df69abc251c84dad64f7015 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/18822 Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/cpu/amd/agesa/family14/model_14_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index ecf1cfb968..3103dd5d3b 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -62,7 +62,7 @@ static void model_14_init(device_t dev) msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); - for (msrno = 0x268; msrno <= 0x26f; i++) + for (msrno = 0x268; msrno <= 0x26f; msrno++) wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); -- cgit v1.2.3