From 5c3f384f064f5c05945d561784fd7e8ef002a295 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 8 May 2014 15:27:15 +0300 Subject: Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines with 'select SERIAL_CPU_INIT' where redundant with the default being yes. Since there is no 'unselect SERIAL_CPU_INIT' possibility, invert the default and rename option. This squelches Kconfig warnings about unmet dependencies. Change-Id: Iae546c56006278489ebae10f2daa627af48abe94 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/5700 Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel --- src/cpu/intel/fsp_model_206ax/Kconfig | 5 +--- src/cpu/intel/haswell/Kconfig | 5 +--- src/cpu/intel/hyperthreading/intel_sibling.c | 2 +- src/cpu/intel/model_2065x/Kconfig | 5 +--- src/cpu/intel/model_206ax/Kconfig | 5 +--- src/cpu/x86/Kconfig | 4 ++-- src/cpu/x86/lapic/lapic_cpu_init.c | 34 ++++++++++++---------------- 7 files changed, 22 insertions(+), 38 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 1db5030013..0fb4437cbd 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -37,16 +37,13 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_LAPIC select SMM_TSEG select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN + select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE config BOOTBLOCK_CPU_INIT string default "cpu/intel/fsp_model_206ax/bootblock.c" -config SERIAL_CPU_INIT - bool - default n - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 60c2066b7e..fa02cba2eb 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -22,16 +22,13 @@ config CPU_SPECIFIC_OPTIONS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select PARALLEL_CPU_INIT select PARALLEL_MP config BOOTBLOCK_CPU_INIT string default "cpu/intel/haswell/bootblock.c" -config SERIAL_CPU_INIT - bool - default n - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index f30ea45da5..d67a5b829f 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -7,7 +7,7 @@ #include #include -#if !CONFIG_SERIAL_CPU_INIT +#if CONFIG_PARALLEL_CPU_INIT #error Intel hyper-threading requires serialized cpu init #endif diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index f59845e5d2..3ef314d711 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select SMM_TSEG select SUPPORT_CPU_UCODE_IN_CBFS + select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE @@ -22,10 +23,6 @@ config BOOTBLOCK_CPU_INIT string default "cpu/intel/model_2065x/bootblock.c" -config SERIAL_CPU_INIT - bool - default n - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index eb45bf8e44..a679e00139 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_LAPIC select SMM_TSEG select SUPPORT_CPU_UCODE_IN_CBFS + select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE @@ -23,10 +24,6 @@ config BOOTBLOCK_CPU_INIT string default "cpu/intel/model_206ax/bootblock.c" -config SERIAL_CPU_INIT - bool - default n - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5c37861214..7689d59ae0 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,6 +1,6 @@ -config SERIAL_CPU_INIT +config PARALLEL_CPU_INIT bool - default y + default n config UDELAY_IO bool diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 2aef2a4bcd..09b6b9eeb0 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -406,9 +406,9 @@ void stop_this_cpu(void) void asmlinkage secondary_cpu_init(unsigned int index) { atomic_inc(&active_cpus); -#if CONFIG_SERIAL_CPU_INIT - spin_lock(&start_cpu_lock); -#endif + + if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) + spin_lock(&start_cpu_lock); #ifdef __SSE3__ /* @@ -421,9 +421,9 @@ void asmlinkage secondary_cpu_init(unsigned int index) write_cr4(cr4_val); #endif cpu_initialize(index); -#if CONFIG_SERIAL_CPU_INIT - spin_unlock(&start_cpu_lock); -#endif + + if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) + spin_unlock(&start_cpu_lock); atomic_dec(&active_cpus); @@ -439,11 +439,9 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) if (cpu->path.type != DEVICE_PATH_APIC) { continue; } - #if !CONFIG_SERIAL_CPU_INIT - if(cpu==bsp_cpu) { + + if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu==bsp_cpu)) continue; - } - #endif if (!cpu->enabled) { continue; @@ -458,9 +456,9 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) printk(BIOS_ERR, "CPU 0x%02x would not start!\n", cpu->path.apic.apic_id); } -#if CONFIG_SERIAL_CPU_INIT - udelay(10); -#endif + + if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) + udelay(10); } } @@ -538,19 +536,17 @@ void initialize_cpus(struct bus *cpu_bus) #endif #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - #if !CONFIG_SERIAL_CPU_INIT /* start all aps at first, so we can init ECC all together */ - start_other_cpus(cpu_bus, info->cpu); - #endif + if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) + start_other_cpus(cpu_bus, info->cpu); #endif /* Initialize the bootstrap processor */ cpu_initialize(0); #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - #if CONFIG_SERIAL_CPU_INIT - start_other_cpus(cpu_bus, info->cpu); - #endif + if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) + start_other_cpus(cpu_bus, info->cpu); /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus); -- cgit v1.2.3