From 5005bb06c17461ef75cd1fef55c24dffaa05e580 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Mon, 11 Apr 2011 20:17:22 +0000 Subject: Unify use of post_code Signed-off-by: Alexandru Gagniuc Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/model_gx2/cache_as_ram.inc | 5 +++-- src/cpu/amd/model_lx/cache_as_ram.inc | 5 +++-- src/cpu/amd/sc520/raminit.c | 6 +++--- src/cpu/intel/car/cache_as_ram.inc | 5 +++-- src/cpu/intel/model_106cx/cache_as_ram.inc | 5 +++-- src/cpu/intel/model_6ex/cache_as_ram.inc | 5 +++-- src/cpu/intel/model_6fx/cache_as_ram.inc | 5 +++-- src/cpu/via/car/cache_as_ram.inc | 5 +++-- src/cpu/x86/32bit/entry32.inc | 3 ++- 9 files changed, 26 insertions(+), 18 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/amd/model_gx2/cache_as_ram.inc b/src/cpu/amd/model_gx2/cache_as_ram.inc index 433576c737..0af2fdf488 100644 --- a/src/cpu/amd/model_gx2/cache_as_ram.inc +++ b/src/cpu/amd/model_gx2/cache_as_ram.inc @@ -27,6 +27,7 @@ #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ #include +#include /*************************************************************************** /** /** DCacheSetup @@ -184,7 +185,7 @@ done_cache_as_ram_main: /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -201,7 +202,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc index a2e8f87e64..a1d775d6d6 100644 --- a/src/cpu/amd/model_lx/cache_as_ram.inc +++ b/src/cpu/amd/model_lx/cache_as_ram.inc @@ -26,6 +26,7 @@ #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ #include +#include /*************************************************************************** /** /** DCacheSetup @@ -210,7 +211,7 @@ done_cache_as_ram_main: /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -227,7 +228,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c index e6232a8eb4..2f7adae190 100644 --- a/src/cpu/amd/sc520/raminit.c +++ b/src/cpu/amd/sc520/raminit.c @@ -144,13 +144,13 @@ void setupsc520(void) /* the 0x80 led should now be working*/ - outb(0xaa, 0x80); + post_code(0xaa); #if 0 - /* wtf are 680 leds ... */ + /* wtf are 680 leds ... *//* <-- WTF is this comment? */ par = (unsigned long *) 0xfffef0c4; *par = 0x28000680; /* well? */ - outb(0x55, 0x80); + post_code(0x55); #endif /* set the uart baud rate clocks to the normal 1.8432 MHz.*/ diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 99c159977e..3949a567c8 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -24,6 +24,7 @@ #include #include #include +#include #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) @@ -364,7 +365,7 @@ lout: /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -375,7 +376,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index d7dba8bf1b..e9820c9aeb 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -20,6 +20,7 @@ #include #include +#include #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -229,7 +230,7 @@ clear_mtrrs: /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -240,7 +241,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index b077ff9a48..fc4947600f 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -20,6 +20,7 @@ #include #include +#include #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -229,7 +230,7 @@ clear_mtrrs: /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -240,7 +241,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 3737429325..a1b82675fb 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -20,6 +20,7 @@ #include #include +#include #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -243,7 +244,7 @@ clear_mtrrs: /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -254,7 +255,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index fcd6c45e5f..6303162cf0 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -27,6 +27,7 @@ #include #include +#include #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE @@ -261,7 +262,7 @@ testok: /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -272,7 +273,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index de3b6cdfaa..740ea47bc7 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -1,6 +1,7 @@ /* For starting coreboot in protected mode */ #include +#include .code32 @@ -51,7 +52,7 @@ __protected_start: /* Save the BIST value */ movl %eax, %ebp - post_code(0x10) + post_code(POST_ENTER_PROTECTED_MODE) movw $ROM_DATA_SEG, %ax movw %ax, %ds -- cgit v1.2.3