From 4f31cdfa2c90e2233e5cdae15961555d9f4abbec Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 28 Oct 2020 22:35:16 +0100 Subject: cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR The MSR only needs to be set when IO MWAIT redirection is to be enabled. This was copied from Sandy Bridge, which already had this inconsistency. Change-Id: I424333afd654db9a7e180e9a2c31d369e3d92fd6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46917 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/haswell_init.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 44bbbfdadf..ff9573f6f8 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -446,12 +446,6 @@ static void configure_c_states(void) /* The deepest package c-state defaults to factory-configured value. */ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); - msr.lo &= ~0xffff; - msr.lo |= (get_pmbase() + 0x14); // LVL_2 base address - /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); - msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination wrmsr(MSR_MISC_PWR_MGMT, msr); -- cgit v1.2.3