From 4913d8aed05d838d5be9c144f7716968ce2962c9 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 5 Aug 2019 12:49:09 +0300 Subject: cpu/x86/smm: Define single smm_subregion() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit At the moment we only have two splitting of TSEG, one with and one without IED. They can all use same implementation. Make configuration problems of TSEG region assertion failures. Rename file from stage_cache.c to tseg_region.c to reflect it's purpose. Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34776 Reviewed-by: Furquan Shaikh Reviewed-by: David Guckian Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/cpu/x86/smm/Makefile.inc | 6 +-- src/cpu/x86/smm/stage_cache.c | 33 ----------------- src/cpu/x86/smm/tseg_region.c | 86 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+), 36 deletions(-) delete mode 100644 src/cpu/x86/smm/stage_cache.c create mode 100644 src/cpu/x86/smm/tseg_region.c (limited to 'src/cpu') diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index fe149f140f..2bb4fd7d3c 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -42,9 +42,9 @@ endif ifeq ($(CONFIG_SMM_TSEG),y) -ramstage-y += stage_cache.c -romstage-y += stage_cache.c -postcar-y += stage_cache.c +ramstage-y += tseg_region.c +romstage-y += tseg_region.c +postcar-y += tseg_region.c smmstub-y += smm_stub.S diff --git a/src/cpu/x86/smm/stage_cache.c b/src/cpu/x86/smm/stage_cache.c deleted file mode 100644 index 0a816ba732..0000000000 --- a/src/cpu/x86/smm/stage_cache.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -int __weak smm_subregion(int sub, uintptr_t *base, size_t *size) -{ - return -1; -} - -void __weak stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c new file mode 100644 index 0000000000..df9dea5c0f --- /dev/null +++ b/src/cpu/x86/smm/tseg_region.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +void __weak smm_region(uintptr_t *start, size_t *size) +{ + *start = 0; + *size = 0; +} + +/* + * Subregions within SMM + * +-------------------------+ + * | IED | IED_REGION_SIZE + * +-------------------------+ + * | External Stage Cache | SMM_RESERVED_SIZE + * +-------------------------+ + * | code and data | + * | (TSEG) | + * +-------------------------+ TSEG + */ +int smm_subregion(int sub, uintptr_t *start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t ied_size = CONFIG_IED_REGION_SIZE; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + smm_region(&sub_base, &sub_size); + + ASSERT(IS_ALIGNED(sub_base, sub_size)); + ASSERT(sub_size > (cache_size + ied_size)); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= ied_size; + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - (ied_size + cache_size); + sub_size = cache_size; + break; + case SMM_SUBREGION_CHIPSET: + /* IED is at the top. */ + sub_base += sub_size - ied_size; + sub_size = ied_size; + break; + default: + *start = 0; + *size = 0; + return -1; + } + + *start = sub_base; + *size = sub_size; + return 0; +} + +void __weak stage_cache_external_region(void **base, size_t *size) +{ + if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) { + printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + *base = NULL; + *size = 0; + } +} -- cgit v1.2.3