From 44ef38f70344f44ee53a3883515246172eb75054 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 25 May 2020 08:52:07 +0300 Subject: arch/x86: Remove NO_FIXED_XIP_ROM_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The variable SETUP_XIP_CACHE provides us a working alternative. Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/amd/agesa/Kconfig | 1 - src/cpu/amd/pi/Kconfig | 1 - src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/model_2065x/Kconfig | 1 - src/cpu/intel/model_206ax/Kconfig | 1 - src/cpu/intel/socket_FCBGA559/Kconfig | 1 - src/cpu/x86/Kconfig | 10 ---------- 7 files changed, 16 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 35e2f93268..3cd387dba7 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_AGESA select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG - select NO_FIXED_XIP_ROM_SIZE select SSE2 if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index bc1253856f..7bcfa61546 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_PI select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG - select NO_FIXED_XIP_ROM_SIZE select SSE2 if CPU_AMD_PI diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index a82198a878..af94314f95 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -22,7 +22,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select NO_FIXED_XIP_ROM_SIZE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index a76a95dc6d..9acde42bcd 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP config SMM_TSEG_SIZE diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index e31260588e..2f0ebf9f50 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP - select NO_FIXED_XIP_ROM_SIZE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index d3af4ca3cc..e6e904dccc 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -11,7 +11,6 @@ config SOCKET_SPECIFIC_OPTIONS select MMX select SSE select CPU_HAS_L2_ENABLE_MSR - select NO_FIXED_XIP_ROM_SIZE config DCACHE_RAM_BASE hex diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 07dfe45e64..5394cd023d 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -60,16 +60,6 @@ config TSC_SYNC_MFENCE to execute an mfence instruction in order to synchronize rdtsc. This is true for all modern Intel CPUs. -config NO_FIXED_XIP_ROM_SIZE - bool - default n - help - The XIP_ROM_SIZE Kconfig variable is used globally on x86 - with the assumption that all chipsets utilize this value. - For the chipsets which do not use the variable it can lead - to unnecessary alignment constraints in cbfs for romstage. - Therefore, allow those chipsets a path to not be burdened. - config SETUP_XIP_CACHE bool depends on !NO_XIP_EARLY_STAGES -- cgit v1.2.3